1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, the present invention relates to the layout structure of interconnection layers which electrically connect elements in semiconductor devices, such as Dynamic Random Access Memories (DRAMs).
2. Description of the Related Art
As multiple metalizations become more frequently utilized in fabricating semiconductor devices, the characteristics of intermediate dielectric films (IMDs) (which provide insulation between adjacent interconnection metal layers) and passivation layers (formed over the wafer) become more important. That is, the IMD must be formed of a material having a low dielectric constant to decrease a parasitic capacitance between adjacent interconnection layers, and also must have good step coverage. The passivation layer, which is an insulating layer that inhibits physical or chemical damage to the uppermost interconnection layer during assembly and packaging, must provide the characteristics enumerated below:
1. Protection of the chip from an external environment, so that the chip operates normally regardless of a type of packaging material utilized and under a severe operating environment, as well as inhibiting differing causes of physical damage. This characteristic is especially pressing in the case of an exposed chip.
2. Protection of the interconnection layers, so that the patterning thereof is not adversely affected by distortion and stress that occurs during operation of the chip. In addition, chemical corrosion of the interconnection layers should be prevented.
3. A low dielectric constant to prevent signal propagation delays caused by parasitic capacitances which accompany the reduced widths of the conductive lines of the interconnection layer.
4. Planarization, i.e., capable of providing a substantially flat upper surface.
To this end, the passivation layer has generally been formed of a silicon nitride (SiN) layer deposited by PECVD (Plasma-Enhanced Chemical Vapor Deposition), and a thick polyimide layer laid thereon. The first passivation SiN layer serves as an impermeable barrier to mobile ions such as Na+, and water, and prevents the chip from being scratched. The second passivation polyimide layer absorbs external impacts, and inhibits the formation of voids which occur in a die bonding process for connecting the metal layer of the bonding pad with the chip package.
However, as the space between adjacent conductive lines of the interconnection layer continues to decrease with the continuing increase in the scale of chip integration, the conventional passivation layer described above inherently suffers various drawbacks. Referring to FIG. 1, the conductive lines 12 of the conventional interconnection layer are arranged in parallel at a constant pitch. In this case, the pitch is defined as the sum of the width of one conductive line and the space between two adjacent conductive lines. With respect to the space between adjacent conductive lines, limitations inherent in CAD and photolithography processes result in this space being wider in the slantwise turning region xe2x80x98Bxe2x80x99 than in the straight line region xe2x80x98Axe2x80x99. As such, as described below, the subsequent passivation process results in a loss of passivation layer material in the wider region.
FIGS. 2A and 2B illustrate the cross sections of the two regions xe2x80x98Axe2x80x99 and xe2x80x98Bxe2x80x99 of FIG. 1 after depositing the nitride passivation layer. A semiconductor substrate (not shown) is firstly covered with an insulating layer 10, on which the conductive lines 12 of the interconnection layer are laid out as shown in FIG. 1, and then an oxide layer 14 is deposited thereon by PECVD. Subsequently, the nitride passivation layer 16 is deposited on the oxide layer 14 by PECVD. In this case, the relatively narrower region xe2x80x98Axe2x80x99 generates the internal cavity 18 caused by the passivation layer 16 crowding the overhead region of the conductive lines 12, while the relatively wider region xe2x80x98Bxe2x80x99 maintains the normal profile of the passivation layer 16 forming the normal gap 20 between the adjacent conductive lines.
The passivation layer 16 is covered with a photoresist layer (not shown), which is exposed to radiation and developed to form a photoresist pattern for defining pad and fuse regions. According to this pattern, the passivation layer 16 and oxide layer 14 are etched to open the pad and fuse regions. During the photolithography, the photoresist in the wider region xe2x80x98Bxe2x80x99 is partially drawn into the cavity 18 of the narrower region xe2x80x98Axe2x80x99 in the direction of arrow xe2x80x98Cxe2x80x99 of FIG. 1, resulting in a loss of the thickness of the photoresist layer in the region xe2x80x98Bxe2x80x99, so that, when etching the passivation layer 16 to open the pad and fuse regions, the part of the passivation layer 16 in the region xe2x80x98Bxe2x80x99 is not protected by the photoresist to generate passivation defects exposing the part of the conductive lines 12 in the region xe2x80x98Bxe2x80x99.
FIGS. 3A and 3B illustrate cross sectional views of the regions xe2x80x98Axe2x80x99 and xe2x80x98Bxe2x80x99 of FIG. 1 after baking the polyimide layer. Even when removing the photoresist pattern used to open the pad and fuse regions by the etching and stripping process, the photoresist part having been drawn into the cavity 18 of the narrower region xe2x80x98Axe2x80x99 cannot be completely removed due to the blocking of the passivation layer 16. After removing the photoresist pattern, the polyimide layer 22 is deposited over it with a thickness of a few xcexcm, and etched to expose the metal of the pad regions. Then, it is baked to harden the polyimide layer 22 at a temperature of about 350xc2x0 C. for about 30 minutes. However, during the baking process, the photoresist residue in the cavity 18 of the narrower region xe2x80x98Axe2x80x99 burns generating pressurized gases moving into the gap between the adjacent conductor lines 12 in the region xe2x80x98Bxe2x80x99, so as to burst the upper polyimide layer 22 as indicated by reference symbol xe2x80x98Dxe2x80x99 in 3B. Consequently, this degrades the reliability of the product. In order to resolve such problem, an additional process or newly proposed passivation layer has been considered, which, however, may cause change of the electrical characteristics of the chip as well as result in increased cost.
It is an object of the present invention to provide a layout structure of the interconnection layers of a semiconductor device, which is devoid of certain procedural defects encountered upon formation of the interconnection layers.
It is another object of the present invention to provide a semiconductor device, which is devoid of certain procedural defects encountered upon depositing a passivation layer in a back-end process.
According to an aspect of the present invention, a layout structure of the interconnection layers includes a plurality of conducting lines extending adjacent one another in a semiconductor device, and at least one rectangular cut-out formed in a side of each of the conducting lines, wherein a width of gap between adjacent ones of the plurality of conducting lines is increased at each rectangular cut-out. Preferably, each rectangular cut-out is dimensioned to achieve a design gap between respective confronting flank portions of an insulating layer which covers adjacent ones of the plurality of conducting lines. The design gap has a predetermined width xcex1, and each rectangular cut-out is dimensioned such that xcex1=Sxe2x88x922T, where S is the increased width between adjacent ones of the plurality of conducting lines, and T is a width of each of the confronting flank portions of the insulating layer. Each rectangular cut-out is located in a region where a space between the adjacent conducting lines is narrow such that in the absence of each rectangular cut-out a cavity would otherwise form in the insulating layer formed over the conducting lines. Preferably, each rectangular cut-out in one of the conducting lines faces towards another rectangular cut-out in an adjacent one of the conducting lines. Also preferably, one rectangular cut-out in one of the conducting lines is opposite another rectangular cut-out in a same one of the conducting lines.
According to another aspect of the present invention, a layout structure of the interconnection layers includes a plurality of conducting lines extending adjacent one another in a semiconductor device, the plurality of conducting lines including a first region in which a spacing between adjacent conducting lines is narrow, and a second region in which a spacing between adjacent conducting lines is wider than in the first region, and at least one rectangular cut-out formed in a side of each of the conducting lines, wherein a width of gap between adjacent ones of the plurality of conducting line is increased at each rectangular cut-out. Preferably, each said rectangular cut-out is located in the first region.
According to still another aspect of the present invention, a semiconductor device includes a cell array region for containing a plurality of memory cells; a peripheral circuit region for containing circuits which drive the memory cells; a plurality of conducting lines extending adjacent one another in a given pattern in the cell array region and peripheral circuit region; a passivation layer formed over the conducting lines; and at least one rectangular cut-out formed in a side of each of the conducting lines. A width of gap between adjacent ones of the plurality of conducting lines is increased at each rectangular cut-out. Preferably, the rectangular cut-out is only arranged in the peripheral circuit region.
Thus, the layout structure of the interconnection layers is modified to selectively increase the space between adjacent conducting lines, so that the procedural defects encountered after depositing the passivation layer can be prevented without applying additional processes or materials, therefore improving the reliability of the chip.